Test Benches

In VHDL, or any HDL for that matter, testing is almost everything! Your VHDL components have no value unless you can evidence that they perform the desired function.

As a general rule, for each component you develop, there should be at least one test bench.

In this series of articles we look at how we use VHDL test benches to test our components.

Part 1 – Testing a Single Architecture Component

Part 2 – Multiple Architectures

Part 3 – Automatic Testing with Assert

Part 4 – Testing with Simulated Timing

Part 5 – Timing Checks

Part 6 – Modelling and Testing Synchronous Systems