Although we do not usually introduce ModelSim early in a course, some students simply prefer it for writing and debugging VHDL. The following video gives a first introduction to using ModelSim.
https://plymouth.cloud.panopto.eu/Panopto/Pages/Viewer.aspx?id=029eec81-2db8-41fc-80ed-aa0e0100890c
Note that it is not common to use ModelSim in interactive mode, but a useful feature none the less.
Next Steps
Vector waveform files are good for beginners. However, you may have noticed how long it takes to perform a full compile and simulation every time you make a change. Contrast this with the rapid compile times in ModelSim, and how it was possible to debug your VHDL interactively. We will learn about VHDL testbenches in year 2 (level 5) where we write VHDL to test components written in VHDL.
If you want to take a look at what is to come, then head over to the next tutorial where I go though ModelSim in much more depth.