I’ve been looking for a simple example of a SPI Slave component in VHDL for some time, and in the end, decided it would be more fun and educational to write my own. To keep the code as clean and simple as possible, I’ve focused entirely on Mode 0 SPI.
I now use this as part of a lab for our stage-2 electronics and robotics students (the lab sheet is included). The connections for a Terasic DE-0 Nano can be found in the reference data folder. The only signals you need to connect across are ground, MOSI, MISO, SCLK and a chip select (CS). You may want to change the signal assignments in the Quartus file.
- The MCU code is written for with classic Mbed and has been exported to Keil uVision. It should work on the free evaluation version.
- The FPGA code is written for Intel Quartus II v18.X, although should work with earlier versions. The free lite edition should be fine.
For anyone interested, the link is shared below. Feel free to clone / fork this as long as you acknowledge the source. If you find any bugs, feel free to raise an issue via GitHub.
https://github.com/UniversityOfPlymouth-Electronics/spi_slave
